1. Field of the Invention.
The present invention relates to semiconductor electronic materials and devices, and, more particularly, to silicon-on-insulator materials and devices and methods of fabrication.
2. Description of the Related Art.
Recently there has been intensive effort to produce electronic quality silicon-on-insulator for very large scale integration applications. See K. Hashimoto et al, Characteristics of Submicrometer CMOS Transistors in Implanted-Buried-Oxide SOI Films, 1985 IEDM Tech. Dig. 672, which notes that silicon-on-insulator technology offers significant potential advantages, such as freedom from latchup in CMOS structures, high packing denisty, low parasitic capacitances, low power, radiation hardness, high voltage operation, and the possibility of three-dimensional integration. Additionally, silicon-on-insulator technology using very thin films offers special advantages for submicron devices. Scaling bulk devices tends to degrade their characteristics because of small-geometry effects, such as punch-through, threshold-voltage shift, and subthreshold-slope degradation; the use of silicon-on-insulator devices suppresses these small-geometry effects. Therefore, even in the submicron VLSI era, silicon-on-insulator technology can offer even higher device performance than can bulk technology, along with the inherent advantages of silicon-on-insulator.
Silicon-on-insulator substrates may be fabricated in various ways: a crystalline silicon layer may be formed over an existing oxide layer either by laser or strip heater recrystallization of polysilicon deposited on the oxide or by selective epitaxial silicon growth over the oxide. However, the quality of such a silicon layer is generally inferior to that normally associated with bulk silicon. Other approaches form an oxide layer beneath an existing high quality silicon layer either by oxidizing a buried porous silicon layer or by oxygen ion implantation; however, such oxide is low quality and the silicon top layer may be damaged during the oxide layer formation.
Another approach to silicon-on-insulator is wafer bonding as described by J. Lasky et al, Silicon-On-Insulator (SOI) by Bonding and Etch-Back, 1985 IEDM Tech. Deg. 684. This wafer bonding process proceeds as follows: a lightly doped epitaxial layer of silicon is grown on a heavily doped silicon substrate, oxide is thermally grown on the epilayer, a second lightly doped silicon substrate is thermally oxidized, the two oxidized surfaces are pressed together and inserted into an oxidizing atmosphere at 1,100.degree. C. to bond them, and a preferential etch is used to remove the heavily doped substrate, leaving the thin, lightly doped epitaxially layer above the bonded thermally grown oxides which are now on the second substrate. The resulting thin silicon layer above the thermally grown oxide has high quality and the oxide also retains its quality and may be thick, as might be desired for CMOS or high voltage devices, or thin, as might be desired for shared element applications. Conceptually, this process may meet all the desired goals for the ultimate silicon-on-insulator material (a specular finished crystalline silicon layer without dislocations and a back interface with the insulator of quality equal to the interface of thermally grown silicon dioxide on silicon; both the crystalline silicon layer and the insulator of variable thickness). However, in practice this process suffers from a serious drawback: a particle between the two mechanically rigid substrate surfaces keeps a substantial area around the particle from bonding. The acute susceptibility of this bonding process to particulate disruption makes the process unattractive for production. Also, the high temperature bonding leads to diffusion of the dopants which degrades the etchstop at the epitaxial layer.
An alternative wafer bonding approach to silicon-on-insulator appears in M. Kimura et al, Epitaxial Film Transfer Technique for Producing Single Crystal Si Film on an Insulating Substrate, 43 Appl. Phys. Lett. 263 (1983). This latter process applies a layer of PbO-B.sub.2 O.sub.3 -SiO.sub.2 glass on each of two oxidized silicon wafers (one wafer being a heavily doped substrate with a lightly doped epilayer) and presses the two glassy surfaces together at 930.degree. C. to bond the wafers; the heavily doped substrate is etched away leaving the epilayer as silicon-on-insulator. Because the wafers must be pressed together at high temperature, this latter process is not suitable for volume production. And the process has the same sensitivity to particulate disruption as previously described.
A similar etchback after forming a secondary substrate method appears in G. Kuhn et al, Thin Silicon Film on Insulating Substrate, 120 J. Electrochem. Soc. 1563 (1973), which forms a thick polysilicon secondary substrate on a silicon substrate with a surface-oxidized lightly doped epilayer on a heavily doped layer; the silicon substrate is then etched away with the heavily doped layer selectively etched to leave the lightly doped epilayer as silicon-on-insulator with the polysilicon secondary substrate as support. However, the polysilicon deposition leads to warping of the silicon substrate and a warped final structure. Also, the polysilicon deposition is performed at high temperature (.apprxeq.1,200.degree. C.) wich diffuses the doped etchstop drastically, thereby preventing the fabrication of thin silicon-on-insulator layers with good control.
The above-mentioned wafer bonding approaches have problems limiting their use in volume production processes for thin silicon-on-insulator layers of high quality.